1. FIELD OF THE INVENTION
The present invention relates to high performance thin film field effect transistors. The transistors include a gate electrode having a non-coplanar surface with respect to a substrate and a deposited semiconductor material overlying the gate electrode forming a short current conduction channel between a source and drain. The deposited semiconductor is electrically insulated from the gate electrode by an insulating oxide which can be annealed prior to the deposition of the semiconductor material.
2. DESCRIPTION OF THE PRIOR ART
Thin film field effect transistors generally comprise source and drain electrodes interconnected by a semiconductor material. Conduction between the electrodes takes place primarily within the semiconductor. The current flow between the electrodes is controlled by the application of a voltage to a gate which is adjacent at least a portion of the semiconductor and is insulated therefrom.
There are many applications wherein it is desirable to have a thin film field effect transistor capable of providing relatively high output currents and operating at relatively high speeds. One such application is in large area liquid crystal displays wherein the transistors are called upon to drive the individual pixels of the displays. The current required to drive these displays is directly related to the display area while the required device speed is directly related to the number of pixels forming the display.
In the film field effect transistors, the device output curren operating speed are largely dependent upon the length of e current conduction channel between the source and drain. Mo particularly, the output current is inversely proportional the channel length and the operating frequency is inversely proportional to the square of the channel length. Hence, if the annel length of a device can be reduced from 10 microns to 1 micron, the output current could be increased ten times and the ating speed could be increased one hundred times. In addition, if the channel length could be decreased as above, the the of the device could be decreased. For example, typical planar thin film field effect transistors have a channel length of 10 microns, a width of about 500 microns and provide current of about 10 microamps. If the channel lengt that device could be reduced to one micron, that same 10 microamps of current could be provided by a device only 50 microns wide. Hence, the total area of the device could be by a factor of ten and thus the packing density could increased by a factor of ten. By reducing the device area by one-tenth, the capacitance of the device can also be reduceo by a factor of ten. Further, the resulting device, while providing the same current and occupying one-tenth the area, could also exhibit an operating frequency one hundred times higher than the original thin film field effect transistors having the ten micron channel.
Unfortunately, the channel length in conventional thin film field effect transistors cannot be readily reduced from the standard channel length of ten microns to a channel length of one micron. The reason for this is that the channel length is determined the spacing between the drain and source electrodes. conventional large area photolithography, the process by which the device structures are formed across twelve inch distances, has a feature size of ten microns. Hence, with conventional photolithography as used for large areas, the minumum channel length obtainable is ten microns.
More precise photolithography having feature sizes down to about one micron are known. However, this precision process is difficult to perform and the equipment necessary to practice it is extremely expensive. In addition, the one micron feature size cannot be maintained over large areas. As a result, while channel lengths in conventional thin film field effect transistors can be reduced to about one micron in the laboratory, it is expensive and cannot be provided over large areas such as is required in large area liquid crystal flat panel displays. This makes precision photolithography virtually useless in commercial applications such as liquid crystal flat panel display where one hundred percent yield over large areas is essential.
To overcome these deficiencies in prior art thin film field effect transistor structures, a new and improved thin film field effect transistor has heen proposed. This improved transistor is disclosed and claimed in commonly assigned and now abandoned copending U.S. application Ser. No. 529,299 for Thin Film Transistor filed in the names of Richard A. Flasck, et al. The transistor therein disclosed includes source and drain regions vertically displaced with respect to each other relative to a substrate and having a channel formed therebetween, the length of which is a function of the vertical displacement distance between the source and drain and which is substantially independent of the constraints otherwise imposed by horizontal lithography.
Further improvement in this transistor is disclosed and claimed in copending U.S. application Ser. No. 549,996, filed concurrently herewith, for High Performance, Small Area, Thin Film Transistor which is assigned to the assignee of the instant invention. The transistor there disclosed includes a drain region, a source region, a gate electrode, a gate insulator, and a deposited semiconductor material. The drain and source region are vertically arrayed with respect to a substrate, have an insulating layer therebetween, and form a non-coplanar surface with respect to the substrate. As defined in that application, a non-coplanar surface is meant to be a surface which defines a plane which is non-parallel with respect to the substrate although it may include minor surface portions which are parallel to the substrate. The deposited semiconductor material which is preferably an amorphous silicon alloy overlies the non-coplanar surface to form a current conduction channel or path between the drain and source regions. The gate electrode insulator overlies the deposited semiconductor and the gate electrode overlies at least a portion of the gate insulator adjacent to the current conduction channel.
These transistor structures exhibit many advantages. Because the thickness of the layer between the source and drain determines the current conduction channel length through the semiconductor, the channel length can be accurately controlled without precision and time consuming photolithography techniques. As a result, short channel lengths are possible providing high current and high speed operation of the device. Further, the accurate control of the short channel lengths can be maintained over large areas for applications such as liquid crystal displays where high yield is essential and where high precision photolithography fails.
While the transistors described above have many advantages, a further improvement thereto is disclosed and claimed in copending U.S. Application Ser. No. 550,234, filed concurrently herewith for High Performance Thin Film Transistor Having Improved Ohmic Contacts and which is assigned to the assignee of the present invention. As described in that application, the drain and source regions are each formed from a layer of a metal, such as molybdenum for example, and a doped semiconductor layer. The doped semiconductor layer provides an enhanced carrier injection and ohmic contact between the deposited semiconductor and the source and drain regions so that higher currents from the device can be obtained for a given source to drain voltage. The enhanced carrier injection and ohmic contacts allow the advantages afforded by the device structure to be fully realized.
The present invention provides a further improvement to these devices. More specifically, the present invention provides a new thin film transistor structure and method of making same wherein the gate oxide can be annealed prior to the deposition of the deposited semiconductor. This is a distinct and significant advantage since annealed oxides exhibit less leakage and fixed charge than oxides which are not annealed. Annealed gate oxides have not been possible in the prior art because the temperature required to effect sufficient annealing would adversely affect the electrical properties of the deposited semiconductor. By virtue of the annealed gate oxide, higher device field mobilities are obtained which increases both the operating frequencies and oulpul current of the devices.